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a ad548 precision, low power bifet op amp features enhanced replacement for lf441 and tl061 dc performance: 200 a max quiescent current 10 pa max bias current, warmed up (ad548c) 250 v max offset voltage (ad548c) 2 v/ c max drift (ad548c) 2 v p-p noise, 0.1 hz to 10 hz ac performance: 1.8 v/ s slew rate 1 mhz unity gain bandwidth available in plastic and hermetic metal can packages and in chip form available in tape and reel in accordance with eia-481a standard mil-std-883b parts available dual version available: ad648 surface-mount (soic) package available product description the ad548 is a low power, precision monolithic operational amplifier. it offers both low bias current (10 pa max, warmed up) and low quiescent current (200 a max) and is fabricated with ion-implanted fet and laser wafer trimming technologies. input bias current is guaranteed over the ad548? entire common-mode voltage range. the economical j grade has a maximum guaranteed input offset voltage of less than 2 mv and an input offset voltage drift of less than 20 v/ c. this level of dc precision is achieved utilizing analog? laser wafer drift trimming process. the combination of low quiescent current and low offset voltage drift minimizes changes in input offset voltage due to self-heating effects. the ad548 is recommended for any dual supply op amp applica- tion requiring low power and excellent dc and ac performance. in applications such as battery-powered, precision instrument front ends and cmos dac buffers, the ad548? excellent com- bination of low input offset voltage and drift, low bias current, and low 1/f noise reduces output errors. high comm on-mode rejection (82 db, min on the ??grade) and high open-loop gain ensures better than 12-bit linearity in high impedance, buffer applications. the ad548 is pinned out in a standard op amp configuration and is available in three performance grades. the ad548j and ad548k are rated over the commercial temperature range of 0 c to 70 c. the ad548b is rated over the industrial tempera- ture range of ?0 c to +85 c. the ad548 is available in an 8-lead plastic mini-dip and sur face-mount (soic) packages. product highlights 1. a combination of low supply current, excellent dc and ac performance and low drift makes the ad548 the ideal op amp for high performance, low power applications. 2. the ad548 is pin compatible with industry standard op amps such as the lf441, tl061, and ad542, enabling designers to improve performance while achieving a reduc tion in power dissipation of up to 85%. 3. guaranteed low input offset voltage (2 mv max) and drift (20 v/ c max) for the ad548j are achieved utilizing analog devices?laser drift trimming technology, eliminating the need for external trimming. 4. analog devices specifies each device in the warmed-up con dition, insuring that the device will meet its published specifications in actual use. 5. a dual version, the ad648, is also available. 6. enhanced replacement for lf441 and tl061. connection diagrams plastic mini-dip (n) package and soic (r)package note: pin 4 connected to case nc = no connect 1 2 3 4 8 7 6 5 ad548 offset null v+ output nc inverting input v offset null top view noninverting input 1 4 5 v os trim top view ?5v 10k rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002
ad548especifications ad548j ad548k/b parameter min typ max min typ max unit input offset voltage 1 initial offset 0.75 2.0 0.3 0.5 mv t min to t max 3.0/3.0/3.0 0.7/0.8 mv vs. temperature 20 5 v/ c vs. supply 80 86 db vs. supply, t min to t max 76/76/76 80 db long-term offset stability 15 15 v/month input bias current either input 2 , v cm = 0 5 20 3 10 pa either input 2 at t max , v cm = 0 0.45/1.3/20 0.25/0.65 na max input bias current over common-mode voltage range 30 15 pa offset current, v cm = 0 5 10 2 5 pa offset current at t max 0.25/0.65/10 0.15/0.35 na input impedance differential 1 10 12 31 10 12 3 pf common mode 3 10 12 33 10 12 3 pf input voltage range differential 3 20 20 v common mode 11 12 11 12 v common-mode rejection v cm = 10 v 76 90 82 92 db t min to t max 76/76/76 90 82 92 db v cm = 11 v 70 84 76 86 db t min to t max 70/70/70 84 76 86 db input voltage noise voltage 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 80 80 nv/ hz hz hz hz hz hz hz hz hz hz hz h
ad548 rev. d ?3? ad548j ad548k/b min typ max min typ max unit power supply rated performance 15 15 v operating range 4.5 18 4.5 18 v quiescent current 170 200 170 200 a temperature range operating, rated performance commercial (0 c to 70 c) ad548j ad548k industrial (e40 c to +85 c) ad548a ad548b military (e55 c to +125 c) ad548s package options soic (r-8) ad548jr ad548kr 4 plastic (n-8) ad548jn 4 ad548kn tape and reel ad548jr-reel ad548kr-reel 4 notes 1 input offset voltage specifications are guaranteed after five minutes of operation at t a = 25 c. 2 bias current specifications are guaranteed maximum at either input after five minutes of operation at t a = 25 c. for higher temperature, the current doubles every 10 c. 3 defined as voltages between inputs, such that neither exceeds 10 v from ground. 4 not recommended for new designs; obsolete april 2002. specifications subject to change without notice. specifications (continued)
ad548 ?4? rev. d warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad548 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings l supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 500 mw input voltage 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and ev s storage temperature range (q, h) . . . . . . . e65 c to +150 c (n, r) . . . . . . . . e65 c to +125 c operating temperature range ad548j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 70 c ad548b . . . . . . . . . . . . . . . . . . . . . . . . . . . . e40 c to +85 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 8-pin soic package: ja = 160 c/w, jc = 42 c/w; 8-lead plastic package: ja = 90 c/w. 3 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage.
supply voltage e v 20 15 10 5 0 input voltage e v 0 5 10 15 20 +v in ev in tpc 1. input voltage range vs. supply voltage supply voltage e v 200 180 160 140 120 quiescent current e a 0 5 10 15 20 tpc 4. quiescent current vs. supply voltage common-mode voltage e v 10 6 4 2 0 input bias current e pa e10 e6 e2 2 6 10 8 tpc 7. input bias current vs. common-mode voltage load resistance e 30 25 20 10 0 10 100 1k 10k 5 15 output voltage swing e v p-p tpc 3. output voltage swing vs. load resistance temperature e c 100na input bias current e55 e25 5 35 65 95 125 10na 1na 100pa 10pa 1pa 100fa 10fa tpc 6. input bias current vs. temperature temperature e c 1500 1000 750 500 0 e55 e25 5 35 65 95 125 1250 250 r l = 10k open loop gain e v/mv tpc 9. open-loop gain vs. temperature supply voltage e v 20 15 10 5 0 output voltage swing e v 0 5 10 15 20 +v out ev out 25 c r l = 10k tpc 2. output voltage swing vs. supply voltage supply voltage e v 10 6 4 2 0 input bias current e pa 0 4 8 12 16 20 8 tpc 5. input bias current vs. supply voltage warm-up time e sec 30 20 15 10 0 0 10 20 30 40 50 60 70 25 5 i v os i e v tpc 8. change in offset voltage vs. warm-up time t ypical performance characteristicse ad548 rev. d ?5?
ad548 ?6? rev. d frequency e hz 100 80 60 0 e40 1k 10k 100k 1m 10m e20 20 40 phase in degrees 100 80 60 0 e40 e20 20 40 phase gain open loop gain e db tpc 10. open-loop frequency response frequency e hz 90 80 70 50 20 1k 10k 100k 1m 40 60 cmrr e db 30 tpc 13. cmrr vs. frequency frequency e hz 4 1 0.001 100 1k 10k 0.01 0.1 total harmonic distortion e % 100k follower with gain = 10 unity gain follower tpc 16. total harmonic distortion vs. frequency frequency e hz 120 100 80 20 e20 100 1k 10k 100k 1m 0 40 60 esupply +supply power supply rejection e db tpc 12. psrr vs. frequency 10mv settling time e s 10 0 e5 e10 output voltage swing e v 0 2 4 6 8 5 1mv 1mv 10mv tpc 15. output swing and error voltage vs. output settling time source impedance e 1,000 100 10 0 100k 1m 10m 100m 1g 10g 100g 10,000 1 amplifier generated noise resistor johnson noise 1khz bandwidth 10hz bandwidth whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for application input noise voltage e v p-p tpc 18. total noise vs. source impedance supply voltage e v 120 100 90 80 60 open loop voltage gain e db 0 2 4 6 8 10 12 14 16 18 110 70 tpc 11. open-loop voltage gain vs. supply voltage output voltage e v p-p frequency e hz 22 20 18 12 8 10 100 1k 10k 100k 1m 10 14 16 0 6 4 2 tpc 14. large signal frequency response frequency e hz 160 140 120 60 20 10 100 1k 10k 100k 40 80 100 0 input noise voltage e nv/ hz tpc 17. input noise voltage spectral density
ad548 tpc 19c. unity gain follower pulse response (small signal) tpc 19b. unity gain follower pulse response (large signal) tpc 20c. unity gain inverter pulse response (small signal) tpc 20b. utility gain inverter pulse response (large signal) application notes the ad548 is a jfet-input op amp with a guaranteed maxi- mum i b of less than 10 pa, and offset and drift laser-trimmed to 0.5 mv and 5 v/ c, respectively (ad548b). ac specs include 1 mhz bandwidth, 1.8 v/ s typical slew rate and 8 s settling time for a 20 v step to 0.01%?all at a supply current less than 200 a. to capitalize on the device?s performance, a number of error sources should be considered. the minimal power drain and low offset drift of the ad548 reduce self-heating or warm-up effects on input offset voltage, making the ad548 ideal for on/off battery-powered applica- tions. the power dissipation due to the ad548?s 200 a supply current has a negligible effect on input current, but heavy out- put loading will raise the chip temperature. since a jfet?s in put current doubles for every 10 c rise in chip temperature, this can be a noticeable effect. the amplifier is designed to be functional with power supply voltages as low as 4.5 v. it will exhibit a higher input offset voltage than at the rated supply voltage of 15 v, due to power supply rejection effects. the common-mode range of the ad548 extends from 3 v more positive than the negative supply to 1 v more negative than the positive supply. designed to cleanly drive up to 10 k and 100 pf loads, the ad548 will drive a 2 k load with reduced open-loop gain. offset nulling unlike bipolar input amplifiers, zeroing the input offset voltage of a bifet op amp will not minimize offset drift. using balance pins 1 and 5 to adjust the input offset voltage as shown in fig ure 1 will induce an added drift of 0.24 v/ c per 100 v of nulled offset. the low initial offset (0.5 mv) of the ad548b results in only 0.6 v/ c of additional drift. rev. d ?7? tpc 19a. unity gain follower tpc 20a. utility gain inverter figure 1. offset null configuration layout to take full advantage of the ad548?s 10 pa max input current, parasitic leakages must be kept below an acceptable level. the practical limit of the resistance of epoxy or phenolic circuit board material is between 1 10 12 and 3 10 12 . this can result in an additional leakage of 5 pa between an input of 0 v and a e15 v supply line. teflon or a similar low leakage mate- rial (with a resistance exceeding 10 17 ) should be used to isolate high impedance input lines from adjacent lines carrying high voltages. the insulator should be kept clean, since con- taminants will degrade the surface resistance. a metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input poten tial can also be used to reduce some parasitic leakages. the guarding pattern in figure 2 will reduce parasitic leakage due to finite board surface resistance; but it will not compensate for a low volume resistivity board. teflon is a registered trademark of dupont.
ad548 ?8? rev. d figure 2. board layout for guarding inputs input protection the ad548 is guaranteed to withstand input voltages equal to the power supply potential. exceeding the negative supply volt- age on either input will forward bias the substrate junction of the chip. the induced current may destroy the amplifier due to excess heat. input protection is required in applications such as a flame detector in a gas chromatograph, where a very high potential may be applied to the input terminals during a sensor fault condition. figure 3 shows a simple current limiting scheme that can be used. r protect should be chosen such that the maxi- mum overload current is 1.0 ma (l00 k for a 100 v overload, for example). exceeding the negative common-mode range on either input terminal causes a phase reversal at the output, forcing the amplifier output to the corresponding high or low state. exceed- ing the negative common-mode on both inputs simultaneously forces the output high. exceeding the positive common-mode range on a single input does not cause a phase reversal, but if both inputs exceed the limit the output will be forced high. in all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range. figure 3. input protection of iv converter d/a converter output buffer the circuit in figure 4 shows the ad548 and ad7545 12-bit cmos d/a converter in a unipolar binary configuration. v out will be equal to v ref attenuated by a factor depending on the digital word. v ref sets the full scale. overall gain is trimmed by adjusting r in . the ad548?s low input offset voltage, low drift, and clean dynamics make it an attractive low power output buffer. the input offset voltage of the ad548 output amplifier results in an output error voltage. this error voltage equals the input offset voltage of the op amp times the noise gain of the am plifier. figure 4. ad548 used as dac output amplifier that is: v os output = v os input 1 + r fb r o
r fb is the feedback resistor for the op amp, which is internal to the dac. r o is the dac?s r-2r ladder output resistance. the value of r o is code dependent. this has the effect of changing the offset error voltage at the amplifier?s output. an output amplifier with a sub millivolt input offset voltage is needed to preserve the linearity of the dac?s transfer function. the ad548 in this configuration provides a 700 khz small signal bandwidth and 1.8 v/ s typical slew rate. the 33 pf capacitor across the feedback resistor optimizes the circuit?s response. the oscilloscope charts in figures 5 and 6 show small and large signal outputs of the circuit in figure 4. upper traces show the input signal v in . lower traces are the resulting output voltage with the dac?s digital input set to all 1s. the ad548 settles to 0.01% for a 20 v input step in 14 s. 0% 10 5v 5s 20v 100 90 figure 5. response to 20 v p-p reference square wave 0% 10 50mv 2s 200mv 100 90 figure 6. response to 100 mv p-p reference square wave
figure 9. low power instrumentation amplifier gains of 1 to 100 can be accommodated with gain nonlinearities of less than 0.01%. input errors, which contribute an output error proportional to in amp gain, include a maximum un trimmed input offset voltage of 0.5 mv and an input offset voltage drift over temperature of 4 v/ c. output errors, which are indepen- dent of gain, will contribute an additional 0.5 mv offset and 4 v/ c drift. the maximum input current is 15 pa over the common-mode range, with a common-mode impedance of over 1 10 12 . resistor pairs r3/r5 and r4/r6 should be ratio matched to 0.01% to take full advantage of the ad548?s high common-mode rejection. capacitors c1 and c1 compen sate for peaking in the gain over frequency caused by input capacitance when gains of 1 to 3 are used. the e3 db small signal bandwidth for this low power instrumenta- tion amplifier is 700 khz for a gain of 1 and 10 khz for a gain of 100. the typical output slew rate is 1.8 v/ s. log ratio amplifier log ratio amplifiers are useful for a variety of signal conditioning applications, such as linearizing exponential transducer outputs and compressing analog signals having a wide dynamic range. the ad548?s picoamp level input current and low input offset voltage make it a good choice for the front-end amplifier of the log ratio circuit shown in figure 10. this circuit produces an output voltage equal to the log base 10 of the ratio of the input currents i 1 and i 2 . resistive inputs r1 and r2 are provided for voltage inputs. input currents i 1 and i 2 set the collector currents of q1 and q2, a matched pair of logging transistors. voltages at points a and b are developed according to the following familiar diode equation: v be = ( kt / q )ln( i c / i es ) in this equation, k is boltzmann?s constant, t is absolute tem- perature, q is an electron charge, and i es is the reverse saturation current of the logging transistors. the difference of these two voltages is taken by the subtractor section and scaled by a factor of approximately 16 by resistors r9, r10, and r8. temperature application hintsead548 photodiode preamp the performance of the photodiode preamp shown in figure 7 is enhanced by the ad548?s low input current, input voltage offset, and offset voltage drift. the photodiode sources a current proportional to the incident light power on its surface. r f converts the photodiode current to an output voltage equal to r f i s . figure 7. an error budget illustrating the importance of low amplifier input current, voltage offset, and offset voltage drift to minimize output voltage errors can be developed by considering the equi- valent circuit for the small (0.2 mm 2 area) photodiode shown in figure 7. the input current results in an error proportional to the feedback resistance used. the amplifier?s offset will produce an error proportional to the preamp?s noise gain (i + r f /r sh ), where r sh is the photodiode shunt resistance. the amplifier?s input current will double with every 10 c rise in temperature, and the photodiode?s shunt resistance halves with every 10 c rise. the error budget in figure 8 assumes a room temperature photodiode r sh of 500 m , and the maximum input current and input offset voltage specs of an ad548c. temp cr sh (m )v os ( v) (1+ r f /r sh ) v os i b (pa) i b r f total e 25 15,970 150 151 v0.3 0 30 v 181 v 0 2,830 200 207 v2 .26 262 v 469 v 25 500 250 300 v 10.00 1.0 mv 1.30 mv 50 88.5 300 640 v 56.6 5.6 mv 6.24 mv 75 15.6 350 2.6 mv 320 32 mv 34.6 mv 85 7.8 370 5.1 mv 640 64 mv 69.1 mv figure 8. photodiode preamp errors over temperature the capacitance at the amplifier?s negative input (the sum of the photodiode?s shunt capacitance, the op amp?s differential input capacitance, stray capacitance due to wiring, etc.) will cause a rise in the preamp?s noise gain over frequency. this can result in excess noise over the bandwidth of interest. c f reduces the noise gain peaking at the expense of bandwidth. instrumentation amplifier the ad548c?s maximum input current of 10 pa makes it an excellent building block for the high input impedance instru- mentation amplifier shown in figure 9. total current drain for this circuit is under 600 a. this configuration is optimal for conditioning differential voltages from high impedance sources. the overall gain of the circuit is controlled by r g , resulting in the following transfer function: v out v in = 1 + ( r 1 + r 2 ) r g rev. d ?9?
ad548 ?10? rev. d figure 10. log ratio amplifier compensation is provided by resistors r8 and r15 that have a positive 3500 ppm/ c temperature coefficient. the transfer function for the output voltage is: v out = 1 v log 10 ( i 2 / i 1 ) frequency compensation is provided by r11, r12, c1, and c2. small signal bandwidth is approximately 300 khz at input cur- rents above 100 a and will proportionally decrease with lower signal levels. d1, d2, r13, and r14 compensate for the effects of the two logging transistors? ohmic emitter resistance. to trim this circuit, set the two input currents to 10 a and ad just v out to zero by adjusting the potentiometer on a3. then set i 2 to 1 a and adjust the scale factor such that the output voltage is 1 v by trimming potentiometer r10. offset adjustment for a1 and a2 is provided to increase the accuracy of the voltage inputs. this circuit ensures a 1% log conformance error over an input current range of 300 pa to 1 ma, with low level accuracy limited by the ad548?s input current. the low level input voltage accu racy of this circuit is limited by the input offset voltage and drift of the ad548.
ad548 rev. d ?11? outline dimensions plastic mini-dip (n) package dimensions shown in inches and (millimeters) soic (r) package dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) pin 1 0.1574 (4.00) 0.1497 (3.80) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012 aa revision history location page data sheet changed from rev. c to rev. d. change to soic (r-8) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 deleted to-99 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 deleted ad548c from specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 deleted metal can from figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 deleted to-99 (h) and cerdip (q) packages from outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
printed in u.s.a. c00510?0?5/02(d) ?12?

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